Invention Grant
- Patent Title: Memory in which the channel potential of a memory cell in a non-selected NAND cell unit is increased
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Application No.: US16251419Application Date: 2019-01-18
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Publication No.: US10720216B2Publication Date: 2020-07-21
- Inventor: Hiroshi Maejima
- Applicant: Toshiba Memory Corporation
- Applicant Address: JP Minato-ku
- Assignee: Toshiba Memory Corporation
- Current Assignee: Toshiba Memory Corporation
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@30c93d4d
- Main IPC: G11C16/10
- IPC: G11C16/10 ; G11C16/04 ; G11C16/08 ; G11C16/34 ; G11C5/02 ; G11C5/06

Abstract:
A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not include a memory cell to be programmed, and programming is executed by applying a program potential or a transfer potential to word lines in the first block after the initial potential of channels of the memory cells in the first and second cell units is set to a plus potential. In the programming, the program potential and the transfer potential are not applied to word lines in the second block.
Public/Granted literature
- US20190172540A1 THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY Public/Granted day:2019-06-06
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