A multilayer ceramic capacitor with decreased high voltage stress defects and a board having the same may include a body formed by stacking a plurality of dielectric layers and a plurality of first and second internal electrodes in a width direction, the first and second internal electrodes including body portions overlapping each other and lead portions exposed to a mounting surface of the body and disposed to be spaced apart from each other, respectively; and first to third external electrodes disposed on the mounting surface of the capacitor body to be connected to the lead portions, respectively, wherein the body portions of the first and second internal electrodes have different areas from each other.