Invention Grant
- Patent Title: Vertical transistors having a layer of charge carriers in the extension region for reduced extension region resistance
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Application No.: US16166384Application Date: 2018-10-22
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Publication No.: US10720502B2Publication Date: 2020-07-21
- Inventor: Takashi Ando , Pouya Hashemi , Choonghyun Lee , Alexander Reznicek , Jingyun Zhang
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Vazken Alexanian
- Main IPC: H01L29/417
- IPC: H01L29/417 ; H01L29/423 ; H01L29/78 ; H01L29/66

Abstract:
Embodiments of the invention are directed to a method of forming a semiconductor device. A non-limiting example of the method includes forming a fin having a fin bottom region. A charged region is formed on a sidewall of the fin bottom region, wherein the charged region includes charged particles, and wherein the fin bottom region is formed from an undoped semiconductor material. The charged particles attract charge carriers in the fin bottom region toward and adjacent to the sidewall of the fin bottom region, wherein the charge carriers form a current path through the undoped semiconductor material of the fin bottom region.
Public/Granted literature
Information query
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