Invention Grant
- Patent Title: Method of controlling wafer bow in a type III-V semiconductor device
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Application No.: US15628723Application Date: 2017-06-21
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Publication No.: US10720520B2Publication Date: 2020-07-21
- Inventor: Seong-Eun Park , Jianwei Wan , Mihir Tungare , Peter Kim , Srinivasan Kannan
- Applicant: Infineon Technologies Austria AG
- Applicant Address: AT Villach
- Assignee: Infineon Technologies Austria AG
- Current Assignee: Infineon Technologies Austria AG
- Current Assignee Address: AT Villach
- Agency: Murphy, Bilak & Homiller, PLLC
- Main IPC: H01L27/14
- IPC: H01L27/14 ; H01L29/778 ; H01L21/02 ; H01L29/267 ; H01L29/20

Abstract:
A type IV semiconductor substrate having a main surface is provided. A type III-V semiconductor channel region that includes a two-dimensional carrier gas is formed over the type IV semiconductor substrate. A type III-V semiconductor lattice transition region that is configured to alleviate mechanical stress arising from lattice mismatch is formed between the type IV semiconductor substrate and the type III-V semiconductor channel region. Forming the type III-V semiconductor lattice transition region includes forming a first lattice transition layer having a first metallic concentration over the type IV semiconductor substrate, forming a third lattice transition layer having a third metallic concentration that is higher than the first metallic concentration over the first lattice transition layer, and forming a fourth lattice transition layer having a fourth metallic concentration that is lower than the first metallic concentration over the third lattice transition layer.
Public/Granted literature
- US20180374941A1 Method of Controlling Wafer Bow in a Type III-V Semiconductor Device Public/Granted day:2018-12-27
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