- Patent Title: Semiconductor device and method of generating power-on reset signal
-
Application No.: US15792758Application Date: 2017-10-25
-
Publication No.: US10720917B2Publication Date: 2020-07-21
- Inventor: Tetsuji Maruyama
- Applicant: LAPIS Semiconductor Co., Ltd.
- Applicant Address: JP Yokohama
- Assignee: LAPIS Semiconductor Co., Ltd.
- Current Assignee: LAPIS Semiconductor Co., Ltd.
- Current Assignee Address: JP Yokohama
- Agency: JCIPRNET
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@671dbe9d
- Main IPC: H03K17/22
- IPC: H03K17/22 ; G06F1/24 ; G06F1/26 ; H03K17/20

Abstract:
A semiconductor device and a method of generating a power-on reset signal are provided. The semiconductor device includes a regulator configured to generate a regulated power supply voltage having a lower voltage value than a power supply voltage based on the power supply voltage and output the regulated power supply voltage to an internal power supply line, and a power-on reset circuit configured to generate a signal which has a first level at which reset is prompted immediately after power for the power supply voltage is turned on and which transitions to a second level at which reset release is prompted from the first level when a voltage value of the internal power supply line has risen as a power-on reset signal.
Public/Granted literature
- US20180123582A1 SEMICONDUCTOR DEVICE AND METHOD OF GENERATING POWER-ON RESET SIGNAL Public/Granted day:2018-05-03
Information query
IPC分类: