Invention Grant
- Patent Title: Selectively disabled output
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Application No.: US15400833Application Date: 2017-01-06
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Publication No.: US10720927B1Publication Date: 2020-07-21
- Inventor: Laura Reese
- Applicant: Altera Corporation
- Applicant Address: US CA San Jose
- Assignee: Altera Corporation
- Current Assignee: Altera Corporation
- Current Assignee Address: US CA San Jose
- Agency: Fletcher Yoder, P.C.
- Main IPC: H03K19/177
- IPC: H03K19/177 ; H03K19/17768 ; H03K19/1776

Abstract:
Circuits, methods, and apparatus are directed to an integrated circuit having a disabling element that can disable a reading of data from the circuit. Once the disabling element is set to not allow a reading of the data, the disabling element cannot be changed to allow a reading of the data. The data may be configuration data or internal data stored within the integrated circuit. Examples of the disabling element include a memory element, a break in a circuit line, and an input pad configuration.
Information query
IPC分类: