Comparator input noise or offset suppression can include an error detector circuit that can operate in a feedback loop, such as during an autozero phase. The error detector circuit can include a time-varying filter response to improve accuracy and convergence time. The comparator can be used in a successive approximation routine (SAR) or other analog-to-digital converter (ADC) circuit, such as to control a digital-to-analog converter (DAC), such as can be used to adjust a tuning circuit within the comparator to compensate for noise or offset. The DAC can be combined with a DAC used for carrying out SAR bit-trials or bit decisions.