Invention Grant
- Patent Title: Semiconductor integrated device and gate screening test method of the same
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Application No.: US15959786Application Date: 2018-04-23
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Publication No.: US10725087B2Publication Date: 2020-07-28
- Inventor: Takahiro Mori , Hitoshi Sumida , Masahiro Sasaki , Akira Nakamori , Masaru Saito , Wataru Tomita , Osamu Sasaki
- Applicant: FUJI ELECTRIC CO., LTD.
- Applicant Address: JP Kawasaki
- Assignee: FUJI ELECTRIC CO., LTD.
- Current Assignee: FUJI ELECTRIC CO., LTD.
- Current Assignee Address: JP Kawasaki
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@70ba63ff
- Main IPC: G01R31/26
- IPC: G01R31/26 ; G05F1/59 ; H03K17/687 ; G01R31/28

Abstract:
To provide a semiconductor integrated device capable of a gate screening test with no need for any additional circuit and without adding any gate screening terminal. The semiconductor integrated device includes a gate drive unit configured to drive the gate of a voltage controlled semiconductor element and a regulator configured to supply a gate drive voltage to the gate drive unit. The regulator includes an external connection terminal capable of receiving a gate screening voltage for the voltage controlled semiconductor element in a gate screening test.
Public/Granted literature
- US20180372791A1 SEMICONDUCTOR INTEGRATED DEVICE AND GATE SCREENING TEST METHOD OF THE SAME Public/Granted day:2018-12-27
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