Invention Grant
- Patent Title: Test circuit and method
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Application No.: US15893466Application Date: 2018-02-09
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Publication No.: US10725090B2Publication Date: 2020-07-28
- Inventor: Mill-Jer Wang , Ching-Nen Peng , Hung-Chih Lin , Sen-Kuei Hsu , Chuan-Ching Wang , Hao Chen
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Cooper Legal Group, LLC
- Main IPC: G01R31/265
- IPC: G01R31/265 ; G01R31/302

Abstract:
A method that is disclosed that includes the operations outlined below. Dies are arranged on a test fixture, and each of the dies includes first antennas and at least one via array, wherein the at least one via array is formed between at least two of the first antennas to separate the first antennas. By the first antennas of the dies, test processes are sequentially performed on an under-test device including second antennas that positionally correspond to the first antennas, according to signal transmissions between the first antennas and the second antennas.
Public/Granted literature
- US20180164365A1 TEST CIRCUIT AND METHOD Public/Granted day:2018-06-14
Information query