A computer processor includes a processor cache that obtains tree data from the memory unit indicative of key values that are pre-sorted in a memory unit. A hardware adaptive merge sort accelerator generates a tournament tree based on the key values, and performs a partial tournament sort that compares a selected key value to a plurality of participating key values to define a sorting path. The hardware adaptive merge sort accelerator also determines an overall winning key value of the partial tournament and a runner-up key value located on the sorting path that is a next lowest key value among the participating key values. The remaining key values are compared to the runner-up key value to sort at least one of the remaining key values in sequential order with respect to the overall winning key value and the runner-up key value.