Invention Grant
- Patent Title: Logical and physical address field size reduction by alignment-constrained writing technique
-
Application No.: US16109504Application Date: 2018-08-22
-
Publication No.: US10725931B2Publication Date: 2020-07-28
- Inventor: Darin Edward Gerhart , Cory Lappi , Nicholas Edward Ortmeier , William Jared Walker
- Applicant: Western Digital Technologies, Inc.
- Applicant Address: US CA San Jose
- Assignee: Western Digital Technologies, Inc.
- Current Assignee: Western Digital Technologies, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Patterson & Sheridan, LLP
- Agent Steven Versteeg
- Main IPC: G06F12/10
- IPC: G06F12/10 ; G06F12/1009 ; G06F3/06

Abstract:
A method and arrangement are disclosed involving receiving a read-type command at a data storage arrangement, calculating a command span of the received read-type command and performing a look-up command, through use of a processor, for data located in each extent at a condensed logical block address state table for the read-type command, wherein the condensed logical block address state table describes a logical to physical table and at least one of transmitting data and displaying data related to the read-type command found in the condensed logical block address state table.
Public/Granted literature
- US20200065258A1 LOGICAL AND PHYSICAL ADDRESS FIELD SIZE REDUCTION BY ALIGNMENT-CONSTRAINED WRITING TECHNIQUE Public/Granted day:2020-02-27
Information query