Disclosed are systems and methods for a compiler, which can receive a computation workload, and a description of the computation graph of the workload and compile a circuit layout of the workload. In one embodiment, an RTL generator assigns the node operations of the computation graph to a first or second type. In the first type, the workload is loaded and processed in tiles equal to a compute filter width. In the second type, the workload is loaded in tiles larger in size than the width of the compute filter, allowing the compute filter to process more operations in parallel and reach the data needed for the underlying operations more efficiently.