Row-determining circuit, DRAM, and method for refreshing a memory array
Abstract:
The present disclosure provides a row-determining circuit. The row-determining circuit includes a plurality of row latches and a target row generator connected to the plurality of row latches. The target row generator is configured to generate a plurality of target row records respectively for a plurality of banks and then send the plurality of target row records respectively to the plurality of row latches. The plurality of row latches are configured to generate a plurality of row address records based on the plurality of target row records.
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