- Patent Title: Structure and method to expose memory cells with different sizes
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Application No.: US16220200Application Date: 2018-12-14
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Publication No.: US10727077B2Publication Date: 2020-07-28
- Inventor: Sheng-Chau Chen , Cheng-Tai Hsiao , Cheng-Yuan Tsai , Hsun-Chung Kuang , Yao-Wen Chang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L43/08
- IPC: H01L43/08 ; H01L21/311 ; H01L45/00 ; H01L21/3105 ; H01L43/02 ; H01L23/528 ; H01L43/12

Abstract:
A memory cell with an etch stop layer is provided. The memory cell comprises a bottom electrode disposed over a substrate. A switching dielectric is disposed over the bottom electrode and having a variable resistance. A top electrode is disposed over the switching dielectric. A sidewall spacer layer extends upwardly along sidewalls of the bottom electrode, the switching dielectric, and the top electrode. A lower etch stop layer is disposed over the lower dielectric layer and lining an outer sidewall of the sidewall spacer layer. The lower etch stop layer is made of a material different from the sidewall spacer layer and protects the top electrode from damaging during manufacturing processes.
Public/Granted literature
- US20190157099A1 STRUCTURE AND METHOD TO EXPOSE MEMORY CELLS WITH DIFFERENT SIZES Public/Granted day:2019-05-23
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