A method of increasing a tolerance to misalignment errors in forming an interconnect via includes: providing a dielectric substrate including at least first and second adjacent metal conductors laterally from one another in a lower metal wiring layer of the integrated circuit; forming a capping layer over at least a portion of an upper surface of the substrate; forming an insulting layer on at least a portion of the capping layer; forming an opening through the insulating and capping layers to expose the first metal conductor; forming a conductive pedestal on the first metal conductor, the conductive pedestal capping an overlay region in the substrate between the first and second metal conductors resulting from misalignment of the opening relative to the first metal conductor; forming a conductive liner on sidewalls of the opening and on the conductive pedestal; and filling the opening with a conductive material to form the via.