Invention Grant
- Patent Title: Integration of single crystalline transistors in back end of line (BEOL)
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Application No.: US16094452Application Date: 2016-06-28
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Publication No.: US10727138B2Publication Date: 2020-07-28
- Inventor: Van H. Le , Marko Radosavljevic , Benjamin Chu-Kung , Rafael Rios , Gilbert Dewey
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- International Application: PCT/US2016/039814 WO 20160628
- International Announcement: WO2018/004537 WO 20180104
- Main IPC: H01L21/84
- IPC: H01L21/84 ; H01L29/423 ; H01L29/417 ; H01L21/822 ; H01L29/41 ; H01L29/775 ; B82Y10/00 ; H01L29/66 ; H01L21/8238 ; H01L29/06 ; H01L21/8234 ; H01L29/786 ; H01L29/08 ; H01L27/06 ; H01L23/00 ; H01L21/768 ; H01L23/522 ; H01L27/12 ; H01L27/092 ; H01L21/02 ; H01L23/532
Abstract:
A monocrystalline semiconductor layer is formed on a conductive layer on an insulating layer on a substrate. The conductive layer is a part of an interconnect layer. The monocrystalline semiconductor layer extends laterally on the insulating layer. Other embodiments may be described and/or claimed.
Public/Granted literature
- US20190131187A1 INTEGRATION OF SINGLE CRYSTALLINE TRANSISTORS IN BACK END OF LINE (BEOL) Public/Granted day:2019-05-02
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