Invention Grant
- Patent Title: Techniques for MRAM top electrode via connection
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Application No.: US16412714Application Date: 2019-05-15
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Publication No.: US10727274B2Publication Date: 2020-07-28
- Inventor: Sheng-Chang Chen , Harry-Hak-Lay Chuang , Hung Cho Wang , Sheng-Huang Huang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L27/22
- IPC: H01L27/22 ; H01L43/10 ; H01L23/52 ; H01L21/768 ; H01L23/532 ; H01L43/02 ; H01F10/32 ; H01L23/522 ; H01L23/528 ; H01L43/12 ; H01F41/32

Abstract:
Some embodiments relate to a memory device. The memory device includes a first magnetoresistive random-access memory (MRAM) cell disposed on a substrate, and a second MRAM cell disposed on the substrate. An inter-level dielectric (ILD) layer is disposed over the substrate. The ILD layer comprises sidewalls defining a trough between the first and second MRAM cells. A dielectric layer disposed over the ILD layer. The dielectric layer completely fills the trough.
Public/Granted literature
- US20200127047A1 TECHNIQUES FOR MRAM TOP ELECTRODE VIA CONNECTION Public/Granted day:2020-04-23
Information query
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