Invention Grant
- Patent Title: Wafer level package and capacitor
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Application No.: US16176506Application Date: 2018-10-31
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Publication No.: US10727295B2Publication Date: 2020-07-28
- Inventor: Tatsuya Funaki , Noriyuki Inoue
- Applicant: Murata Manufacturing Co., Ltd.
- Applicant Address: JP Nagaokakyo-Shi, Kyoto-Fu
- Assignee: MURATA MANUFACTURING CO., LTD.
- Current Assignee: MURATA MANUFACTURING CO., LTD.
- Current Assignee Address: JP Nagaokakyo-Shi, Kyoto-Fu
- Agency: Arent Fox LLP
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@22eb03d5
- Main IPC: H01L29/00
- IPC: H01L29/00 ; H01L49/02 ; H01G4/33 ; H01G4/12 ; H01L21/56 ; H01L23/525 ; H01L23/522 ; H01L23/00 ; H01L23/12 ; H01L23/48 ; H01L23/498 ; H01L23/31

Abstract:
A wafer level package which includes an IC chip; a rewiring layer on the IC chip; and a capacitor embedded in the rewiring layer.
Public/Granted literature
- US20190074347A1 WAFER LEVEL PACKAGE AND CAPACITOR Public/Granted day:2019-03-07
Information query
IPC分类: