A signal processing system includes: a transmission channel; a common-mode signal transmitting circuit configured to output an uplink signal to the transmission channel in a common mode; a common-mode signal detecting circuit configured to detect a common-mode signal from the uplink signal transmitted by the transmission channel; a downlink reference clock signal generating circuit configured to generate a downlink reference clock signal at a second frequency with reference to the first clock edge of the common-mode signal detected by the common-mode signal detecting circuit; a downlink data generating circuit configured to generate downlink data; a differential signal transmitting circuit configured to output, as a downlink signal, the downlink data generated by the downlink data generating circuit to the transmission channel in a differential mode; and a differential signal receiving circuit configured to extract a differential signal from the downlink signal.