Invention Grant
- Patent Title: Processor to execute shift right merge instructions
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Application No.: US16208534Application Date: 2018-12-03
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Publication No.: US10732973B2Publication Date: 2020-08-04
- Inventor: Julien Sebot , William W. Macy, Jr. , Eric L. Debes , Huy V. Nguyen
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Nicholson De Vos Webster & Elliott LLP
- Main IPC: G06F9/30
- IPC: G06F9/30 ; G06F9/38 ; G06F17/14 ; G06F17/15 ; G06F15/80

Abstract:
Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.
Public/Granted literature
- US20190220280A1 PROCESSOR TO EXECUTE SHIFT RIGHT MERGE INSTRUCTIONS Public/Granted day:2019-07-18
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