Invention Grant
- Patent Title: Migrating operating system interference events to a second set of logical processors along with a set of timers that are synchronized using a global clock
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Application No.: US15685506Application Date: 2017-08-24
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Publication No.: US10733032B2Publication Date: 2020-08-04
- Inventor: John Divirgilio , Liana L. Fong , John Lewars , Seetharami R. Seelam , Brian F. Veale
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Fleit Intellectual Property Law
- Agent Thomas S. Grzesik
- Main IPC: G06F9/54
- IPC: G06F9/54 ; G06F9/38 ; G06F9/48

Abstract:
A method, information processing system, and computer program product are provided for managing operating system interference on applications in a parallel processing system. A mapping of hardware multi-threading threads to at least one processing core is determined, and first and second sets of logical processors of the at least one processing core are determined. The first set includes at least one of the logical processors of the at least one processing core, and the second set includes at least one of a remainder of the logical processors of the at least one processing core. A processor schedules application tasks only on the logical processors of the first set of logical processors of the at least one processing core. Operating system interference events are scheduled only on the logical processors of the second set of logical processors of the at least one processing core.
Public/Granted literature
- US20170371725A1 HARDWARE MULTI-THREADING CO-SCHEDULING FOR PARALLEL PROCESSING SYSTEMS Public/Granted day:2017-12-28
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