A processor core executes a first instruction indicating a first coherence state update policy that biases the cache memory to retain write authority, thereafter executes a second instruction indicating a second coherence state update policy that biases the cache memory to transfer write authority, and executes a store instruction following the first instruction in program order to generate a store request. A cache memory stores the cache line in association with a coherence state field set to a first modified coherence state. In response to the store request, the cache memory updates data of the cache line. If the store instruction is executed prior to the second instruction, the cache memory refrains from updating the coherence state field, but if the store instruction is executed after the second instruction, the cache memory updates the coherence state field from the first modified coherence state to a second modified coherence state.