Invention Grant
- Patent Title: Latency optimized I3C virtual GPIO with configurable operating mode and device skip
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Application No.: US16392264Application Date: 2019-04-23
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Publication No.: US10733121B2Publication Date: 2020-08-04
- Inventor: Lalan Jee Mishra , Radu Pitigoi-Aron , Richard Dominic Wietfeldt , Sharon Graif , Lior Amarilio , Kishalay Haldar , Oren Nishry
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Loza & Loza LLP
- Main IPC: G06F9/455
- IPC: G06F9/455 ; G06F13/20 ; G06F13/42

Abstract:
Systems, methods, and apparatus for communicating virtual GPIO information generated at multiple source devices and directed to multiple destination devices. A method performed at a device coupled to a serial bus includes generating first virtual GPIO state information representative of state of one or more physical GPIO output pins, asserting a request to transmit the first virtual GPIO state information by driving a data line of the serial bus from a first state to a second state after a start code has been transmitted on a serial bus and before a first clock pulse is transmitted on a clock line of the serial bus, transmitting the first virtual GPIO state information as a first set of bits in a data frame associated with the start code, and receiving second virtual GPIO state information in a second set of bits in the data frame.
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