- Patent Title: Integrated circuit and layout method for standard cell structures
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Application No.: US15965358Application Date: 2018-04-27
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Publication No.: US10733352B2Publication Date: 2020-08-04
- Inventor: Sheng-Hsiung Chen , Chung-Te Lin , Fong-Yuan Chang , Ho Che Yu , Li-Chun Tien
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Sterne, Kessler, Goldstein & Fox P.L.L.C.
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F30/398 ; H01L27/02 ; H01L27/118 ; G06F30/394

Abstract:
Placement methods described in this disclosure provide placement and routing rules where a system implementing the automatic placement and routing (APR) method arranges standard cell structures in a vertical direction that is perpendicular to the fins but parallel to the cell height. Layout methods described in this disclosure also improve device density and further reduce cell height by incorporating vertical power supply lines into standard cell structures. Pin connections can be used to electrically connect the power supply lines to standard cell structures, thus improving device density and performance. The APR process is also configured to rotate standard cells to optimize device layout.
Public/Granted literature
- US20190155984A1 INTEGRATED CIRCUIT AND LAYOUT METHOD FOR STANDARD CELL STRUCTURES Public/Granted day:2019-05-23
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