A write-in date circuit in a semiconductor device may include multiple input buffers, each receiving multiple data bits in a serial data stream. The circuit may include a first circuit coupled to a first and a second input buffers. The first circuit may be further coupled to receive a DQS signal and latch a first data bit selected from the first input buffer or the second input buffer responsive to the DQS signal. The second circuit may be coupled to the first and second input buffers and configured to latch a second data bit selected from the first input buffer or the second input buffer responsive to the DQS signal. The first circuit may latch the first data bit responsive to a rising edge of the DQS signal and the second circuit may latch the second data bit responsive to a falling edge of the DQS signal.