Three terminal isolation elements and methods
Abstract:
A monolithic three-dimensional memory array is provided that includes a plurality of global bit lines disposed above a substrate, a plurality of vertically-oriented bit lines disposed above the global bit lines, a plurality of word lines disposed above the global bit lines, a plurality of memory cells coupled between the vertically-oriented bit lines and the word lines, and a plurality of isolation elements coupled between the vertically-oriented bit lines and the global bit lines. Each isolation element includes a vertical thin-film transistor and a threshold selector device.
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