Invention Grant
- Patent Title: Metal cut patterning and etching to minimize interlayer dielectric layer loss
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Application No.: US15845652Application Date: 2017-12-18
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Publication No.: US10734234B2Publication Date: 2020-08-04
- Inventor: Kisup Chung , Ekmini Anuja De Silva , Andrew Greene , Siva Kanakasabapathy , Indira Seshadri
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Amin, Turocy & Watson, LLP
- Main IPC: H01L21/28
- IPC: H01L21/28 ; H01L29/51

Abstract:
The present disclosure relates to methods and apparatuses related to the deposition of a protective layer selective to an interlayer dielectric layer so that the protective layer is formed onto a top portion associated with the interlayer dielectric layer. In some embodiments, a method comprises: forming an interlayer dielectric layer on a substrate; covering a trench region with a metal liner, wherein the trench region is situated above the substrate and formed within the interlayer dielectric layer; and depositing a protective layer selective to the interlayer dielectric layer so that the protective layer is formed onto a top portion associated with the interlayer dielectric layer. In various embodiments, the depositing the protective layer comprises: repeatedly depositing the protective layer via a multi-deposition sequence; or depositing a self-assembled monolayer onto the top portion.
Public/Granted literature
- US20190189452A1 METAL CUT PATTERNING AND ETCHING TO MINIMIZE INTERLAYER DIELECTRIC LAYER LOSS Public/Granted day:2019-06-20
Information query
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