Invention Grant
- Patent Title: Poly gate extension design methodology to improve CMOS performance in dual stress liner process flow
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Application No.: US16167903Application Date: 2018-10-23
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Publication No.: US10734290B2Publication Date: 2020-08-04
- Inventor: Younsung Choi , Steven Lee Prins
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Jacqueline J. Garner; Charles A. Brill; Frank D. Cimino
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L27/092 ; H01L29/78 ; H01L29/423 ; H01L27/02

Abstract:
An integrated circuit and method with dual stress liners and with NMOS transistors with gate overhang of active that is longer than the minimum design rule and with PMOS transistors with gate overhang of active that are not longer than the minimum design rule.
Public/Granted literature
- US20190057904A1 POLY GATE EXTENSION DESIGN METHODOLOGY TO IMPROVE CMOS PERFORMANCE IN DUAL STRESS LINER PROCESS FLOW Public/Granted day:2019-02-21
Information query
IPC分类: