Invention Grant
- Patent Title: Packaged integrated circuit having stacked die and method for therefor
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Application No.: US16038684Application Date: 2018-07-18
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Publication No.: US10734312B2Publication Date: 2020-08-04
- Inventor: Burton Jesse Carpenter , Kim Roger Gauen
- Applicant: NXP USA, INC.
- Applicant Address: US TX Austin
- Assignee: NXP USA, Inc.
- Current Assignee: NXP USA, Inc.
- Current Assignee Address: US TX Austin
- Main IPC: H01L23/495
- IPC: H01L23/495 ; H01L23/00 ; H01L23/62 ; H01L21/56 ; H01L25/065 ; H01L23/522 ; H04B5/00 ; H01L23/31

Abstract:
A packaged integrated circuit (IC) device includes a first set of stacked die having a first IC die, a first inductor in the first IC die, an isolation layer over the first IC die, a second IC die over the isolation layer, and a second inductor in the second IC die aligned to communicate with the first inductor, and a second set of stacked die having a third IC die, a third inductor in the third IC die, a second isolation layer over the third IC die, a fourth IC die over the second isolation layer, and a fourth inductor in the fourth IC die aligned to communicate with the third inductor. The isolation layer extends a prespecified distance beyond a first edge of the second IC die, and the second isolation layer extends a second prespecified distance beyond a first edge of the fourth IC die.
Public/Granted literature
- US20200027823A1 PACKAGED INTEGRATED CIRCUIT HAVING STACKED DIE AND METHOD FOR THEREFOR Public/Granted day:2020-01-23
Information query
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