Invention Grant
- Patent Title: Via structure for packaging and a method of forming
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Application No.: US16665919Application Date: 2019-10-28
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Publication No.: US10734341B2Publication Date: 2020-08-04
- Inventor: Ming-Che Ho , Yi-Wen Wu , Chien Ling Hwang , Hung-Jui Kuo , Chung-Shi Liu
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/56
- IPC: H01L21/56 ; H01L23/00 ; H01L27/112 ; H01L23/31 ; H01L21/48 ; H01L21/3105 ; H01L25/065 ; H01L27/02
Abstract:
A via or pillar structure, and a method of forming, is provided. In an embodiment, a polymer layer is formed having openings exposing portions of an underlying conductive pad. A conductive layer is formed over the polymer layer, filling the openings. The dies are covered with a molding material and a planarization process is performed to form pillars in the openings. In another embodiment, pillars are formed and then a polymer layer is formed over the pillars. The dies are covered with a molding material and a planarization process is performed to expose the pillars. In yet another embodiment, pillars are formed and a molding material is formed directly over the pillars. A planarization process is performed to expose the pillars. In still yet another embodiment, bumps are formed and a molding material is formed directly over the bumps. A planarization process is performed to expose the bumps.
Public/Granted literature
- US20200058613A1 Via Structure for Packaging and a Method of Forming Public/Granted day:2020-02-20
Information query
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