Invention Grant
- Patent Title: Vertical transport static random-access memory cells with transistors of active regions arranged in linear rows
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Application No.: US15923683Application Date: 2018-03-16
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Publication No.: US10734372B2Publication Date: 2020-08-04
- Inventor: Brent A. Anderson , Stuart A. Sieg , Junli Wang
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Ryan, Mason & Lewis, LLP
- Agent Vazken Alexanian
- Main IPC: H01L27/02
- IPC: H01L27/02 ; H01L27/11 ; H01L27/092 ; H01L29/06 ; H01L29/423 ; H01L21/8238 ; H01L29/786 ; H01L21/02 ; G11C11/41 ; G11C11/412

Abstract:
A semiconductor structure includes a vertical transport static random-access memory (SRAM) cell having a first active region and a second active region. The first active region and the second active region are linearly arranged in first and second rows, respectively. The first row of the first active region includes a first pull-up transistor, a first pull-down transistor and a first pass gate transistor, and the second row of the second active region includes a second pull-up transistor, a second pull-down transistor and a second pass gate transistor. A first gate region of the first active region extends orthogonal from the first row to the second active region, and a second gate region of the second active region extends orthogonal from the second row to the first active region.
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