Vertical transport static random-access memory cells with transistors of active regions arranged in linear rows
Abstract:
A semiconductor structure includes a vertical transport static random-access memory (SRAM) cell having a first active region and a second active region. The first active region and the second active region are linearly arranged in first and second rows, respectively. The first row of the first active region includes a first pull-up transistor, a first pull-down transistor and a first pass gate transistor, and the second row of the second active region includes a second pull-up transistor, a second pull-down transistor and a second pass gate transistor. A first gate region of the first active region extends orthogonal from the first row to the second active region, and a second gate region of the second active region extends orthogonal from the second row to the first active region.
Information query
Patent Agency Ranking
0/0