Invention Grant
- Patent Title: Semiconductor device
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Application No.: US16544101Application Date: 2019-08-19
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Publication No.: US10734374B2Publication Date: 2020-08-04
- Inventor: Takeshi Okagaki , Koji Shibutani , Makoto Yabuuchi , Nobuhiro Tsuda
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Koutou-ku, Tokyo
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Koutou-ku, Tokyo
- Agency: Sughrue Mion, PLLC
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@8d1ba72 com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@4d0e7d47
- Main IPC: H01L27/02
- IPC: H01L27/02 ; H01L27/092 ; G06F30/394 ; H01L29/417

Abstract:
An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured.
Public/Granted literature
- US20190378831A1 SEMICONDUCTOR DEVICE Public/Granted day:2019-12-12
Information query
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