Invention Grant
- Patent Title: Horizontal gate all-around device having wrapped-around source and drain
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Application No.: US16155387Application Date: 2018-10-09
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Publication No.: US10734500B2Publication Date: 2020-08-04
- Inventor: Chun-Hsiung Lin , Chung-Cheng Wu , Carlos H. Diaz , Chih-Hao Wang , Wen-Hsing Hsieh , Yi-Ming Sheu
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L29/417
- IPC: H01L29/417 ; H01L29/66 ; H01L21/8234 ; H01L27/088 ; H01L29/423 ; H01L29/78

Abstract:
Various transistors, such as horizontal gate-all-around transistors, and methods of fabricating such are disclosed herein. An exemplary transistor includes a first nanowire and a second nanowire that include a first semiconductor material, a gate that wraps a channel region of the first nanowire and the second nanowire, and source/drain feature that wraps source/drain regions of the first nanowire and the second nanowire. The source/drain feature includes a second semiconductor material that is configured differently than the first semiconductor material. In some implementations, the transistor further includes a fin-like semiconductor layer disposed over a substrate. The first nanowire and the second nanowire are disposed over the fin-like semiconductor layer, such that the first nanowire, the second nanowire, and the fin-like semiconductor layer extend substantially parallel to one another along the same length-wise direction. The fin-like semiconductor layer includes a third semiconductor material that is configured differently than the first semiconductor material.
Public/Granted literature
- US20190051734A1 Horizontal Gate All-Around Device Having Wrapped-Around Source and Drain Public/Granted day:2019-02-14
Information query
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