Invention Grant
- Patent Title: MOS devices having epitaxy regions with reduced facets
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Application No.: US16592050Application Date: 2019-10-03
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Publication No.: US10734520B2Publication Date: 2020-08-04
- Inventor: Hsueh-Chang Sung , Kun-Mu Li , Tze-Liang Lee , Chii-Horng Li , Tsz-Mei Kwok
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/66 ; H01L29/165 ; H01L21/8234 ; H01L29/417 ; H01L21/28 ; H01L27/088 ; H01L21/02 ; H01L21/285 ; H01L21/768
Abstract:
An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region. The second silicon germanium region comprises a portion in the opening. The second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap substantially free from germanium is over the second silicon germanium region.
Public/Granted literature
- US20200035831A1 MOS DEVICES HAVING EPITAXY REGIONS WITH REDUCED FACETS Public/Granted day:2020-01-30
Information query
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