Invention Grant
- Patent Title: Enhanced immunity latched logic state retention
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Application No.: US16236330Application Date: 2018-12-28
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Publication No.: US10734978B2Publication Date: 2020-08-04
- Inventor: Soman Purushothaman , Sankar Prasad Debnath , Per Torstein Roine , Steven C. Bartling , Keshav Bhaktavatson Chintamani
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Brian D. Graham; Charles A. Brill; Frank D. Cimino
- Main IPC: H03K3/037
- IPC: H03K3/037 ; H03K3/012
Abstract:
In described examples, a latch includes circuitry for latching input information. The circuitry can be precharged in response to an indication of a first mode and can latch the input information to an indication of a second mode. The latch can optionally further latch the input information in response to a node for storing the latched input information.
Public/Granted literature
- US20200212896A1 ENHANCED IMMUNITY LATCHED LOGIC STATE RETENTION Public/Granted day:2020-07-02
Information query
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