Invention Grant
- Patent Title: Conditional construct splitting for latency hiding
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Application No.: US16227741Application Date: 2018-12-20
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Publication No.: US10740074B2Publication Date: 2020-08-11
- Inventor: Brian J. Favela , Todd Martin , Robert A. Gottlieb
- Applicant: ADVANCED MICRO DEVICES, INC.
- Applicant Address: US CA Santa Clara
- Assignee: ADVANCED MICRO DEVICES, INC.
- Current Assignee: ADVANCED MICRO DEVICES, INC.
- Current Assignee Address: US CA Santa Clara
- Main IPC: G06F8/41
- IPC: G06F8/41 ; G06T1/20

Abstract:
A method and system for compiler optimization includes analyzing a representation of source code to identify an original conditional construct having both a high-latency instruction and one or more instructions dependent on the high-latency instruction in a branch of the conditional construct. A set of one or more instructions following the conditional construct in the representation of source code and independent of the high-latency instruction is selected. An optimized representation of the source code is generated, whereby the optimized representation replaces the original conditional construct with a first split conditional construct positioned prior to the selected set of one or more instructions and a second split conditional construct positioned following the selected set of one or more instructions, The method further includes generating an executable representation of the source code based on the optimized representation of the source code.
Public/Granted literature
- US20200174761A1 CONDITIONAL CONSTRUCT SPLITTING FOR LATENCY HIDING Public/Granted day:2020-06-04
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