A circuit includes a memory configured to store a data unit and parity bits, the parity bits being based on a write address associated with the stored data unit. An address port is configured to receive a read address for the stored data unit. A decoding circuit is configured to generate a decoded write address from the read address and the parity bits, and an error detecting circuit is configured to determine if an address error exists based on a comparison of the decoded write address to the read address.