Invention Grant
- Patent Title: Method for accessing entry in translation lookaside buffer TLB and processing chip
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Application No.: US16211225Application Date: 2018-12-05
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Publication No.: US10740247B2Publication Date: 2020-08-11
- Inventor: Weiguang Cai , Xiongli Gu , Lei Fang
- Applicant: HUAWEI TECHNOLOGIES CO., LTD.
- Applicant Address: CN Shenzhen, Guangdong
- Assignee: HUAWEI TECHNOLOGIES CO., LTD.
- Current Assignee: HUAWEI TECHNOLOGIES CO., LTD.
- Current Assignee Address: CN Shenzhen, Guangdong
- Agency: Womble Bond Dickinson (US) LLP
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F13/00 ; G06F12/1027

Abstract:
A method for accessing an entry in a translation lookaside buffer and a processing chip are provided. In the method, the entry includes at least one combination entry, and the combination entry includes a virtual huge page number, a bit vector field, and a physical huge page number. The physical huge page number is an identifier of N consecutive physical pages corresponding to the N consecutive virtual pages. One entry is used to represent a plurality of virtual-to-physical page mappings, so that when a page table length is fixed, a quantity of entries in the TLB can be increased exponentially, thereby increasing a TLB hit probability, and reducing TLB misses. In this way, a delay in program processing can be reduced, and processing efficiency of the processing chip can be improved.
Public/Granted literature
- US20190108134A1 METHOD FOR ACCESSING ENTRY IN TRANSLATION LOOKASIDE BUFFER TLB AND PROCESSING CHIP Public/Granted day:2019-04-11
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