Invention Grant
- Patent Title: Programmable logic integrated circuit, design support system, and configuration method
-
Application No.: US15576947Application Date: 2016-05-23
-
Publication No.: US10740435B2Publication Date: 2020-08-11
- Inventor: Noboru Sakimura , Yukihide Tsuji , Ayuka Tada , Xu Bai , Makoto Miyamura , Ryusuke Nebashi
- Applicant: NEC Corporation
- Applicant Address: JP Tokyo
- Assignee: NEC CORPORATION
- Current Assignee: NEC CORPORATION
- Current Assignee Address: JP Tokyo
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@3933801d
- International Application: PCT/JP2016/002495 WO 20160523
- International Announcement: WO2016/194332 WO 20161208
- Main IPC: G06F17/50
- IPC: G06F17/50 ; H03K19/17732 ; H03K19/173 ; G11C29/00 ; G11C13/00 ; G11C7/22 ; H03K19/003

Abstract:
Provided is a programmable logic integrated circuit wherein even if a failure occurs in any resistance-variable element, remedy would be possible and hence the improvement of reliability has been achieved. In a programmable logic integrated circuit comprising resistance-variable elements, when the states of the resistance-variable elements are to be changed according to externally inputted configuration information, a control means uses a reading means to read the states of the respective resistance-variable elements, and then uses a writing means to change only the states of resistance-changing elements that are different from a state indicated by the configuration information.
Public/Granted literature
- US20180157779A1 PROGRAMMABLE LOGIC INTEGRATED CIRCUIT, DESIGN SUPPORT SYSTEM, AND CONFIGURATION METHOD Public/Granted day:2018-06-07
Information query