Aspects of the present disclosure address improved systems and methods for generating a clock tree based on route-driven placement of fan-out clock drivers. Consistent with some embodiments, a method may include constructing a spanning tree comprising one or more paths that interconnect a set of clock sinks of a clock net of an integrated circuit device design. The method further includes calculating a center of the set of the clock sinks based on clock sink locations in the integrated circuit device design and identifying a point on the spanning tree nearest to the center of the set of clock sinks. The method further includes generating a clock tree by placing a clock driver at the point on the spanning tree that is nearest to the center of the set of clock sinks.