An apparatus is disclosed. The apparatus includes an address counter configured to provide a refresh address to a refresh circuit, wherein the address counter includes a plurality of counter cells coupled in series from a first counter cell to a last counter cell downstream of the first counter cell, wherein an output of each of the plurality of counter cells each correspond to an address bit of the refresh address, wherein the address bit of the refresh address provided by a later counter cell downstream of an earlier counter cell is a less significant bit of the refresh address than the address bit of the refresh address provided by the earlier counter cell.