Disclosed is a computer memory including a memory array, an address decoder, and a wordline enable circuit. The wordline enable circuit includes a plurality of memory cells, each cell corresponding to a memory row of the memory array. Each memory cell stores a flag indicating whether a data row of the corresponding memory row should have a value of zero. The wordline enable circuit additionally includes multiple outputs, each corresponding to a memory row of the memory array. The wordline enable circuit outputs a signal having the first value (e.g., 1 or HI) through an output corresponding to the input address in response to receiving an input signal having the first value and the flag being stored by the memory cell corresponding to the input address having a first flag value.