Invention Grant
- Patent Title: Method for forming interconnect structure
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Application No.: US15828077Application Date: 2017-11-30
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Publication No.: US10741417B2Publication Date: 2020-08-11
- Inventor: Hsi-Wen Tien , Wei-Hao Liao , Chih-Wei Lu , Pin-Ren Dai , Chung-Ju Lee
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Maschoff Brennan
- Main IPC: H01L21/48
- IPC: H01L21/48 ; H01L23/532 ; H01L23/522 ; H01L23/528

Abstract:
A method for forming an interconnect structure is provided. The method includes: forming a dielectric layer on a substrate, and forming an opening in the dielectric layer; forming a first metal layer, a second metal layer, and a third metal layer sequentially over the dielectric layer. The opening of the dielectric layer is filled with the first metal layer to form a conductive via. The method also includes: performing one or multiple etch operation to etch the first metal layer, the second metal layer, and the third metal layer, so as to form a metal line corresponding to the first metal layer, an intermediate metal layer corresponding to the second metal layer, and a metal pillar corresponding to the third metal layer. In particular, the width of the metal line is greater than the width of the metal pillar.
Public/Granted literature
- US20190164781A1 METHOD FOR FORMING INTERCONNECT STRUCTURE Public/Granted day:2019-05-30
Information query
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