Invention Grant
- Patent Title: Barrier layer formation for conductive feature
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Application No.: US15993751Application Date: 2018-05-31
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Publication No.: US10741442B2Publication Date: 2020-08-11
- Inventor: Chia-Pang Kuo , Ya-Lien Lee
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/532 ; H01L21/02 ; H01L23/528 ; H01L21/285 ; H01L29/45 ; H01L21/3205

Abstract:
Embodiments described herein relate generally to one or more methods for forming a barrier layer for a conductive feature in semiconductor processing. In some embodiments, an opening is formed through a dielectric layer to a conductive feature. A barrier layer is formed in the opening along a sidewall of the dielectric layer and on a surface of the conductive feature. Forming the barrier layer includes depositing a layer including using a precursor gas. The precursor gas has a first incubation time for deposition on the surface of the conductive feature and has a second incubation time for deposition on the sidewall of the dielectric layer. The first incubation time is greater than the second incubation time. A conductive fill material is formed in the opening and on the barrier layer.
Public/Granted literature
- US20190371660A1 BARRIER LAYER FORMATION FOR CONDUCTIVE FEATURE Public/Granted day:2019-12-05
Information query
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