Invention Grant
- Patent Title: Structure and method to reduce shorts and contact resistance in semiconductor devices
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Application No.: US15873946Application Date: 2018-01-18
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Publication No.: US10741495B2Publication Date: 2020-08-11
- Inventor: Sunil K. Singh , Vinit O. Todi , Shao Beng Law
- Applicant: GLOBALFOUNDRIES INC.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Gibb & Riley, LLC
- Agent Anthony J. Canale
- Main IPC: H01L23/522
- IPC: H01L23/522 ; H01L23/532 ; H01L21/3105 ; H01L21/311 ; H01L21/768

Abstract:
In an exemplary method, a first dielectric layer is formed on a substrate. A second dielectric layer is formed on the first dielectric layer. The second dielectric layer is a carbon rich film and different from the first dielectric layer. A trench is formed through the first and second dielectric layers. A conductive line is formed in the trench. A third dielectric layer is formed on the second dielectric layer and conductive line. The material of the third dielectric layer is different from the second dielectric layer. A via opening is formed through the third dielectric layer and stops at the second dielectric layer with a portion of the conductive line exposed to the via opening. At the bottom of the via opening, a recess is formed in the second dielectric layer adjacent to the conductive line. The via opening and recess are filled with a conductive material contacting the conductive line.
Public/Granted literature
- US20190221523A1 STRUCTURE AND METHOD TO REDUCE SHORTS AND CONTACT RESISTANCE IN SEMICONDUCTOR DEVICES Public/Granted day:2019-07-18
Information query
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