- Patent Title: Semiconductor device manufacturing method and semiconductor wafer
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Application No.: US15833315Application Date: 2017-12-06
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Publication No.: US10741504B2Publication Date: 2020-08-11
- Inventor: Takuji Yoshida
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Mattingly & Malur, PC
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@7c228337
- Main IPC: H01L23/535
- IPC: H01L23/535 ; H01L23/58 ; H01L21/304 ; H01L21/78 ; B24B37/04 ; H01L23/00 ; H01L21/683 ; H01L29/66 ; H01L29/06 ; H01L29/40 ; H01L29/423 ; H01L29/10 ; H01L29/739 ; H01L23/528

Abstract:
A semiconductor wafer provided with a pseudo chip between a product chip and a pattern prohibiting region is prepared. With the edge portion of the semiconductor wafer left, the bottom surface of the inner semiconductor substrate is ground, and then, the semiconductor wafer is cut in a ring shape to remove the edge portion. Here, in the pseudo chip, a protective film covering the conductive pattern is formed on the top surface of the semiconductor substrate and the end surface of the protective film facing the pattern prohibiting region is positioned on the conductive pattern. Further, in plan view, the inner peripheral end of the edge portion is positioned in the pattern prohibiting region, and the pattern prohibiting region between the inner peripheral end of the edge portion and the pseudo chip is cut in a ring shape.
Public/Granted literature
- US20180197825A1 SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR WAFER Public/Granted day:2018-07-12
Information query
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