The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip has a source region and a drain region. The drain region is separated from the source region by a channel region. An isolation structure surrounds the source region, the drain region, and the channel region. A gate structure is over the channel region. The gate structure includes a first gate electrode region having one or more first materials and a second gate electrode region having one or more second materials that are different than the one or more first materials. The second gate electrode region continuously extends between a first outermost sidewall directly over the isolation structure and a second outermost sidewall directly over the channel region.