Invention Grant
- Patent Title: Semiconductor structures and fabrication methods thereof
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Application No.: US16113067Application Date: 2018-08-27
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Publication No.: US10741670B2Publication Date: 2020-08-11
- Inventor: Fei Zhou
- Applicant: Semiconductor Manufacturing International (Shanghai) Corporation , Semiconductor Manufacturing International (Beijing) Corporation
- Applicant Address: CN Shanghai CN Beijing
- Assignee: Semiconductor Manufacturing International (Shanghai) Corporation,Semiconductor Manufacturing International (Beijing) Corporation
- Current Assignee: Semiconductor Manufacturing International (Shanghai) Corporation,Semiconductor Manufacturing International (Beijing) Corporation
- Current Assignee Address: CN Shanghai CN Beijing
- Agency: Anova Law Group, PLLC
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@4f44d01d
- Main IPC: H01L21/311
- IPC: H01L21/311 ; H01L21/8238 ; H01L21/02 ; H01L27/02 ; H01L27/092 ; H01L29/66 ; H01L29/40 ; H01L21/321 ; H01L21/762 ; H01L29/417 ; H01L29/06 ; H01L21/3213 ; H01L21/3105 ; H01L29/78 ; H01L21/265

Abstract:
A method for fabricating a semiconductor device includes providing a semiconductor structure including a semiconductor substrate, a plurality of semiconductor fin structures, and a plurality of dummy gate structures, each including a dummy insulating layer and a dummy gate electrode; forming a covering layer including a first portion on side surfaces of each dummy gate structure and a second portion on semiconductor fin structures; forming a sacrificial layer on side surfaces of the first portion of the covering layer; forming a first trench and a second trench on two opposite sides of each dummy gate structure; forming a source electrode in each first trench and a drain electrode in each second trench; forming an interlayer dielectric layer; performing a planarization process to expose dummy gate structures; and removing each dummy gate electrode and a portion of the dummy insulating layer to form a trench to expose the semiconductor fin structure.
Public/Granted literature
- US20190067449A1 SEMICONDUCTOR STRUCTURES AND FABRICATION METHODS THEREOF Public/Granted day:2019-02-28
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