Invention Grant
- Patent Title: Trench DMOS transistor with reduced gate-to-drain capacitance
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Application No.: US15645479Application Date: 2017-07-10
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Publication No.: US10741687B2Publication Date: 2020-08-11
- Inventor: Yaojian Leng , Richard Foote , Steven J. Adler
- Applicant: National Semiconductor Corporation
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Jacqueline J. Garner; Charles A. Brill; Frank D. Cimino
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/06 ; H01L29/66 ; H01L29/423

Abstract:
A trench DMOS transistor with a very low on-state drain-to-source resistance and a high gate-to-drain charge includes one or more floating islands that lie between the gate and drain to reduce the charge coupling between the gate and drain, and effectively lower the gate-to-drain capacitance.
Public/Granted literature
- US20170309743A1 TRENCH DMOS TRANSISTOR WITH REDUCED GATE-TO-DRAIN CAPACITANCE Public/Granted day:2017-10-26
Information query
IPC分类: