A programmable clock divider having reset circuits configured to receive a DP count comprises a first flip-flop having a clock input, a first output, and one of the DP inputs configured to receive a clock signal, a plurality of flip-flops connected to form a ripple counter configured to each receive a DP input, a clock input, and a reset input to provide a first output coupled to the clock input of a subsequent flip-flop of the plurality of flip-flops, each subsequent flip-flop having its clock input coupled to the first output of the preceding flip-flop, a first reset circuit coupled to the flip-flops configured to provide an out signal in response to the flip-flops obtaining the DP count, and a second reset circuit configured to provide a reset signal to the reset input of the plurality of flip-flops in response to the out signal from the first reset circuit.